PXR40RM Datasheet, PDF (1347/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Nexus Development Interface (NDI)
31.10.4 Features
The NZ7C3 module is compliant with Class 3 of the IEEE-ISTO 5001-2011 standard. The following
features are implemented:
• Program trace via branch trace messaging (BTM). Branch trace messaging displays program flow
discontinuities (direct and indirect branches, exceptions, etc.), allowing the development tool to
interpolate what transpires between the discontinuities. Thus static code can be traced.
• Data trace via data write messaging (DWM) and data read messaging (DRM). This provides the
capability for the development tool to trace reads and/or writes to selected internal memory
resources.
• Ownership trace via ownership trace messaging (OTM). OTM facilitates ownership trace by
providing visibility of which process ID or operating system task is activated. An ownership trace
message is transmitted when a new process/task is activated, allowing the development tool to
trace ownership flow.
• Run-time access to embedded processor registers and memory map via the JTAG port. This allows
for enhanced download/upload capabilities.
• Watchpoint messaging via the auxiliary pins.
• Watchpoint trigger enable of program and/or data trace messaging.
• High-speed data input/output via the auxiliary port.
• Auxiliary interface for higher data input/output
— Configurable (minimum and maximum) message data out pins
— One read/write ready pin
— One watchpoint-event pin
— One event-in pin
— One MCKO (message clock out) pin
• Registers for program trace, data trace, ownership trace and watchpoint trigger.
• All features controllable and configurable via the JTAG port.
31.10.5 Enabling Nexus3 Operation
The Nexus module is enabled by loading a single instruction (ACCESS_AUX_TAP_ONCE, as shown in
Table 31-4) into the JTAGC instruction register (IR), and then loading the corresponding OnCE OCMD
register with the NEXUS3_ACCESS instruction (see Table 31-5). For the e200z7 Class 3 Nexus module,
the OCMD value is 0b00_0111_1100. After it is enabled, the module is ready to accept control input via
the JTAG pins. See Section 31.7, NPC Functional Description, for more information.
The Nexus module is disabled when the JTAG state machine reaches the test-logic-reset state. This state
can be reached by asserting the JCOMP pin or cycling through the state machine using the TMS pin. The
Nexus module is also disabled if a power-on-reset (POR) event occurs. If the Nexus3 module is disabled,
no trace output is provided, and the module disables (drive inactive) auxiliary port output pins MDO[n:0],
MSEO[1:0], MCKO. Nexus registers are not available for reads or writes.
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
31-31