PXR40RM Datasheet, PDF (302/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Interrupts and Interrupt Controller (INTC)
10.1.2 Overview
Interrupt functionality for the device is handled between the e200z7 core and the interrupt controller. The
CPU core has 19 exception sources, each of which can interrupt the core. One exception source is from
the interrupt controller (INTC). The INTC provides priority-based scheduling of interrupt requests and
supports programmable preemption. This scheduling scheme is suitable for statically scheduled hard
real-time systems. The INTC is optimized for a large number of interrupt requests.
Table 10-1 displays the interrupt sources and the number of interrupts available for each module;
Figure 10-2 shows a general diagram of INTC software vector mode.
Table 10-1. Interrupt Sources Available
Interrupt Source (IRQs)
Number of
Interrupts Available
Software
8
Watchdog
1
Memory
1
eDMA
99
FMPLL
2
External IRQ input pins (SIU)
6
eMIOS
32
eTPU engine A
33
eTPU engine B
32
eQADC
62
DSPI
20
eSCI
3
FlexCAN
84
FlexRay
8
STM
2
Decimation Filter
16
System (PIT, RTI, PMC, etc.)
7
10-2
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor