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PXR40RM Datasheet, PDF (46/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller | |||
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Introduction
⢠64-bit general-purpose registers (GPRs) support vector instructions defined by the SPE2 APU
â All arithmetic instructions that execute in the core operate on data in the GPRs
⢠Enhanced signal processing extension (SPE2) APU supports real-time fixed point and
single-precision embedded numerics operations using the GPRs
⢠Variable length encoding (VLE) enhancements
â Allows optional encoding of mixed 16-bit and 32-bit instructions
â Results in smaller code size footprint
â Minimizes impact on performance
⢠Six read and three write operations per clock
â Integrates a pair of integer execution units, a branch control unit, instruction fetch unit and
load/store unit, and a multi-ported register file
⢠Branch target prefetching performed by the branch unit allows single-cycle branches in many cases
⢠16 KB instruction cache and 16 KB data cache, both supporting error detection hardware.
⢠Memory management unit (MMU) with 64-entry fully-associative translation look-aside buffer (TLB)
⢠Nexus Class 3+ module
⢠Supports non-maskable interrupt (completely un-maskable and not guaranteed to be recoverable)
and critical interrupt (an interrupt that can be masked and is guaranteed to be recoverable) sources
â Routed from a single package pin, via edge detection logic in the SIU, to the CPU
⢠An additional Wait for Interrupt instruction:
â Used in conjunction with low power STOP mode
â Instruction stops the system clock
â An external interrupt source or the system wake-up timer restart the system clock, allowing the
CPU to service the interrupt
⢠Includes multiple input signature register (MISR) hardware which can be accessed by software to
implement CPU self test functionality
1.2.4 On-chip flash memory
The PXR40 flash memory module provides the following:
⢠4 MB of programmable, non-volatile, flash memory
â Nonvolatile memory (NVM) can be used for instruction and/or data storage
⢠A fetch accelerator optimizes the performance of the flash memory array to match the CPU
architecture
â Architected to optimize the performance of the flash memory with the CPU to provide
single-cycle random access to the flash memory when in full clock mode, and two-cycle access
when in double clock mode
â Configurable read buffering and line prefetch support
⢠An interface between the system bus and a dedicated flash memory array controller
PXR40 Microcontroller Reference Manual, Rev. 1
1-6
Freescale Semiconductor
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