PXR40RM Datasheet, PDF (978/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Serial Communication Interface (eSCI)
26.4.6.5.5 Slave-Not-Responding-Error Detection
The Slave-Not-Responding-Error is defined in LIN Specification Package Revision 1.3; December 12,
2002; 6 ERROR AND EXCEPTION HANDLING. The LIN specification requires that a
NO_RESPONSE_ERROR has to be detected if a message frame is not fully completed within the
maximum length T_{FRAME_MAX} by any slave task upon transmission of the SYNCH and IDENTIFIER
fields. The maximum frame length TFRAME_MAX is defined in LIN Specification Package Revision
1.3; December 12, 2002; 3.3 LENGTH OF MESSAGE FRAME AND BUS SLEEP DETECT, as
T_{FRAME_MAX} = 10  N_DATA + 45  1.4
Eqn. 26-11
where N_DATA is the number of data byte fields of the message frame.
The STO interrupt flag in the Interrupt Flag and Status Register 2 (eSCI_IFSR2) will be set, if an LIN RX
frame was not fully received in the amount of time specified in the timeout value field TO in the LIN
Transmit Register (eSCI_LTR). The time period starts with the falling edge of the transmitted LIN break
character and is specified in units of transmit bits.
To achieve LIN compliant Slave-Not-Responding-Error detection, the timeout value TO in the LIN
Transmit Register (eSCI_LTR) field has to be set to T_{FRAME_MAX} when a LIN RX frame is initiated.
26.4.6.5.6 Checksum Error Detection
If the checksum enable bit CSE in the LIN Transmit Register (eSCI_LTR) was set, the checksum checking
is performed based on the received checksum byte. The checksum mode is selected by the CSM bit in the
LIN Transmit Register (eSCI_LTR). If the value received in the checksum bytes did not match the
calculated checksum, the checksum error flag CKERR in the Interrupt Flag and Status Register
2 (eSCI_IFSR2) will be set.
26.4.6.5.7 CRC Error Detection
The CRC checking is performed on the two received CRC bytes CRC1 and CRC2 if the CRC Enhanced
LIN frame format was selected by the CRC bit in the LIN Transmit Register (eSCI_LTR). If the value
received in the two CRC bytes did not match the calculated CRC pattern, the CRC error flag CERR in the
Interrupt Flag and Status Register 2 (eSCI_IFSR2) will be set.
26.4.6.5.8 Overflow Detection
When the receiver has received the next byte field, which should be transferred into the LIN Receive
Register (eSCI_LRR), but neither the application nor the RX DMA channel have read data from this
register since the last update, the received data overflow flag OVFL in the Interrupt Flag and Status
Register 2 (eSCI_IFSR2) will be set. In this case the content of the LIN Receive Register (eSCI_LRR) is
not changed. The data received most recently are lost.
26.4.6.6 LIN Wakeup
The section describes the LIN Wakeup behavior of the eSCi module.
26-50
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor