PXR40RM Datasheet, PDF (552/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Direct Memory Access Controller (eDMA)
Field
0
NOP
1–7
CERR
Offset: EDMA_x_BASE + 0x001D
Access: User write-only
0
1
2
3
4
5
6
7
R0
0
0
0
0
0
0
0
W NOP
CERR[0:6]
Reset 0
0
0
0
0
0
0
0
Figure 21-14. eDMA Clear Error Register (EDMA_x_CER)
Table 21-13. EDMA_x_CER Field Descriptions
Description
No operation.
0 Normal operation.
1 No operation, ignore bits 1–7.
Clear Error Indicator.
0–31 (63 for eDMA_A) Clear corresponding bit in EDMA_A_ERH or EDMA_x_ERL.
64–127 Clear all bits in EDMA_A_ERH or EDMA_x_ERL.
Bit 2 (CER[1]) is not used on eDMA_B.
21.3.2.11 eDMA Set START Bit Register (EDMA_x_SSBR)
The EDMA_x_SSBR provides a memory-mapped mechanism to set the START bit in the TCD of the
given channel. The data value on a register write causes the START bit in the corresponding transfer
control descriptor to be set. Setting bit 1 (SSB[0]) provides a global set function, forcing all START bits
to be set. Reads of this register return all zeroes.
If bit 0 is set, the SSB command is ignored. This allows multiple byte registers to be written as a 32-bit
word. Reads of this register return all zeroes.
Offset: EDMA_x_BASE + 0x001E
Access: User write-only
0
1
2
3
4
5
6
7
R0
0
0
0
0
0
0
0
W NOP
SSB[0:6]
Reset 0
0
0
0
0
0
0
0
Figure 21-15. eDMA Set START Bit Register (EDMA_x_SSBR)
21-28
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor