PXR40RM Datasheet, PDF (626/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

FlexRay Communication Controller (FLEXRAY)
Field
SFTOR
Table 22-38. SFTOR Field Description
Description
Sync Frame Table Offset — The offset of the Sync Frame Tables in the Flexray Memory. This offset is required
to be 16-bit aligned. Thus STF_OFFSET[0] is always 0.
22.5.2.33 Sync Frame Table Configuration, Control, Status Register (SFTCCSR)
Base + 0x0044
Write: Normal Mode
0
1
2
R0
0
W ELKT OLKT
Reset 0
0
0
3
4
5
6
CYCNUM
0
0
0
0
7
8
9
10
11
12
13
14
15
ELKS OLKS EVAL OVAL 0
0 _{SDV SID}
OPT ^{EN EN}
0
0
0
0
0
0
0
0
0
Figure 22-33. Sync Frame Table Configuration, Control, Status Register (SFTCCSR)
This register provides configuration, control, and status information related to the generation and access
of the clock sync ID tables and clock sync measurement tables. For a detailed description, see
Section 22.6.12, Sync Frame ID and Sync Frame Deviation Tables.
Table 22-39. SFTCCSR Field Descriptions
Field
ELKT
OLKT
CYCNUM
ELKS
OLKS
EVAL
OVAL
Description
Even Cycle Tables Lock/Unlock Trigger — This trigger bit is used to lock and unlock the even cycle tables.
0 No effect
1 Triggers lock/unlock of the even cycle tables.
Odd Cycle Tables Lock/Unlock Trigger — This trigger bit is used to lock and unlock the odd cycle tables.
0 No effect
1 Triggers lock/unlock of the odd cycle tables.
Cycle Number — This field provides the number of the cycle in which the currently locked table was
recorded. If none or both tables are locked, this value is related to the even cycle table.
Even Cycle Tables Lock Status — This status bit indicates whether the application has locked the even
cycle tables.
0 Application has not locked the even cycle tables.
1 Application has locked the even cycle tables.
Odd Cycle Tables Lock Status — This status bit indicates whether the application has locked the odd cycle
tables.
0 Application has not locked the odd cycle tables.
1 Application has locked the odd cycle tables.
Even Cycle Tables Valid — This status bit indicates whether the Sync Frame ID and Sync Frame Deviation
Tables for the even cycle are valid. The controller clears this status bit when it starts updating the tables, and
sets this bit when it has finished the table update.
0 Tables are not valid (update is ongoing)
1 Tables are valid (consistent).
Odd Cycle Tables Valid — This status bit indicates whether the Sync Frame ID and Sync Frame Deviation
Tables for the odd cycle are valid. The controller clears this status bit when it starts updating the tables, and
sets this bit when it has finished the table update.
0 Tables are not valid (update is ongoing)
1 Tables are valid (consistent).
22-42
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor