PXR40RM Datasheet, PDF (1269/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

External Bus Interface (EBI)
30.2.3.5 D_ADD_DAT [0:31] — Data Lines 0-31
The D_ADD_DAT[0:31] signals contain the data to be transferred for the current transaction.
D_ADD_DAT[0:31] is driven by the EBI when it owns the external bus and it initiates a write transaction
to an external device.
D_ADD_DAT[0:31] is driven by an external device during a read transaction from the EBI.
For 8-bit and 16-bit transactions, the byte lanes not selected for the transfer do not supply valid data.
D_ADD_DAT[0:31] is driven by the EBI in the address phase with the D_ADD value if the Address on
Data multiplexing mode is enabled. See Section 30.1.4.6, Multiplexed Address on Data Bus Mode, for
details.
In 16-bit Data Bus Mode, (or for chip-select accesses to a 16-bit port), only D_ADD_DAT[0:15] or
D_ADD_DAT[16:31] are used by the EBI, depending on the setting of the D16_31 bit in the EBI_MCR.
See Section 30.1.4.5, 16-Bit Data Bus Mode.
30.2.3.6 D_OE — Output Enable
D_OE is used to indicate when an external memory is permitted to drive back read data. External
memories must have their data output buffers off when D_OE is negated. D_OE is only asserted for
chip-select accesses.
For read cycles, D_OE is asserted one clock after D_TS assertion and held until the termination of the
transfer. For write cycles, D_OE is negated throughout the cycle.
30.2.3.7 D_RD_WR — Read / Write
D_RD_WR indicates whether the current transaction is a read access or a write access.
D_RD_WR is driven in the same clock as the assertion of D_TS and valid address, and is kept valid until
the cycle is terminated.
30.2.3.8 D_TA — Transfer Acknowledge
D_TA is asserted to indicate that the slave has received the data (and completed the access) for a write
cycle, or returned data for a read cycle. If the transaction is a burst read, D_TA is asserted for each one of
the transaction beats. For write transactions, D_TA is only asserted once at access completion, even if more
than one write data beat is transferred.
D_TA is driven by the EBI when the access is controlled by the chip selects (and SETA=0). Otherwise,
D_TA is driven by the slave device to which the current transaction was addressed.
See Section 30.4.2.8, Termination Signals Protocol for more details.
30.2.3.9 D_TEA — Transfer Error Acknowledge
D_TEA is asserted by either the EBI or an external device to indicate that an error condition has occurred
during the bus cycle.
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
30-7