PXR40RM Datasheet, PDF (169/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Frequency Modulated Phase-Locked Loop (FMPLL)
Table 6-6. ESYNCR2 Bit Field Descriptions (continued)
Field
Description
26–31
ERFD
Enhanced Reduced Frequency Divider. The ERFD bits control a divider at the output of the PLL. The value
specified by the ERFD bits establish the divisor applied to the PLL frequency. The ERFD divides the output
clock by the quantity (ERFD + 1). Even-numbered ERFD settings, which would result in odd divide ratios, are
not allowed.
The decimal equivalent of the ERFD binary number is substituted into the equation from Table 6-10.
Note: The ERFD divides the output clock by the quantity (ERFD + 1). Even numbered ERFD settings, which
would result in odd divide ratios, are invalid and cause the PLL to produce an unpredictable output
clock. The PLL output clock must be within the f_PLL specification (see the PXR40 Microcontroller Data
Sheet).
Changing the ERFD bits does not affect the PLL, hence, no re-lock delay is incurred. Resulting changes in
clock frequency are synchronized to the next falling edge of the current system clock. These bits should be
written only when the lock bit (LOCK) is set, to avoid surpassing the allowable system operating frequency.
In PLL Off mode, the ERFD bits have no effect.
The available output divider ratios are given in Table 6-8.
1 _{ERATE and EDEPTH must be enabled simultaneously to avoid unintentional assertion of the LOLF. Program the desired}
modulation rate and depth to the ERATE and EDEPTH bit fields simultaneously with a single 32 bit write to the ESYNCR2
register.
2 _{Auto-calibration is not available on the PXR40 device. EDEPTH does not set modulation depth and is used only in conjunction}
with the SYNFMCR[FMDAC_EN] to enable FM. See Section 6.4.3.4, PLL Normal Mode With Frequency Modulation”.
Table 6-7. Programmable Modulation Rates
ERATE
00
01
10
11
Modulation Rate (Hz)
F_mod = F_extal/80
F_mod = F_extal/40
F_mod = F_extal/20
Invalid
Table 6-8. Output Divide Ratios
ERFD
00_0000
00_0001
00_0010
00_0011
00_0100
00_0101
00_0110
00_0111
Output Divide Ratio (ERFD+1)
Divide-by-1
Divide-by-2
Invalid
Divide-by-4
Invalid
Divide-by-6
Invalid
Divide-by-8
(default value for PXR40)
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
6-11