PXR40RM Datasheet, PDF (1067/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Queued Analog-to-Digital Converter (EQADC)
Table 27-39. Command FIFO Status Switching Condition (continued)
From Current
No.
CFIFO Status
(CFS)
To New CFIFO
Status (CFS)
Status Switching Condition
7 TRIGGERED (11)
IDLE (0b00)
— CFIFO in single-scan mode, EQADC detects the EOQ bit
asserted at end of command transfer, and CFIFO Mode is not
modified to disabled.OR
— CFIFO, in single-scan level trigger mode, and the gate
closes while no commands are being transferred from the
CFIFO, and CFIFO Mode is not modified to disabled. OR
— CFIFO, in single-scan level trigger mode, and EQADC
detects a closed gated at end of command transfer, and CFIFO
Mode is not modified to disabled. OR
— CFIFO Mode is modified to disabled mode and CFIFO was
not transferring commands.
—CFIFO Mode is modified to disabled mode while CFIFO was
transferring commands, and CFIFO completes or aborts the
transfer.
8
WAITING FOR — CFIFO in single or continuous-scan edge trigger mode,
TRIGGER (0b10) EQADC detects the Pause bit asserted at the end of command
transfer, the EOQ bit in the same command is negated, and
CFIFO Mode is not modified to disabled, OR
— CFIFO in continuous-scan edge trigger mode, EQADC
detects the EOQ bit asserted at the end of command transfer,
and CFIFO Mode is not modified to disabled, OR
— CFIFO, in continuous-scan level trigger mode, and the gate
closes while no commands are being transferred from the
CFIFO, and CFIFO Mode is not modified to disabled, OR
— CFIFO, in continuous-scan level trigger mode, and EQADC
detects a closed gated at end of command transfer, and CFIFO
Mode is not modified to disabled.
9
TRIGGERED — No event to switch to IDLE or WAITING FOR TRIGGER
(0b11)
status has happened.
27.7.4.7.2 CQueue Completion Status
The End of Queue Flag (EOQF) in Section 27.6.2.7, EQADC FIFO and Interrupt Status Registers
(EQADC_FISR), is asserted when the EQADC completes the transfer of a CFIFO entry with an asserted
EOQ bit. Software sets the EOQ bit in the last Command Message of a CQueue to indicate that this entry
is the end of the CQueue - see Section 27.7.2.2, Message Format in EQADC, for information on command
message formats. The transfer of entries bound for the on-chip ADCs is considered completed when they
are stored in the appropriate CBuffer.
The command with a EOQ bit asserted is valid and will be transferred. When EOQIE in Section 27.6.2.5,
EQADC CFIFO Control Registers (EQADC_CFCR), and EOQF are asserted, the EQADC will generate
an End of Queue interrupt request.
In single-scan modes, command transfers from the corresponding CFIFO will cease when EQADC
completes the transfer of a entry with an asserted EOQ. Software involvement is required to rearm the
CFIFO so that it can detect new trigger events.
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
27-85