PXR40RM Datasheet, PDF (964/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Serial Communication Interface (eSCI)
If an idle character has been detected, the IDLE flag in the Interrupt Flag and Status Register 1
(eSCI_IFSR1) is set. If the idle line interrupt enable bit ILIE in the Control Register 1 (eSCI_CR1) is set,
the IDLE interrupt request is generated.
If any of the receiver errors described in Section 26.4.5.4, Reception Error Reporting, have been occurred,
that corresponding flags will be set.
If the application disabled the receiver by clearing the receiver enable bit RE in the Interrupt Flag and
Status Register 1 (eSCI_IFSR1) the current frame is discarded and no flags will be updated.
26.4.5.3.10 DMA Controlled SCI Data Frames Reception
In this mode, the eSCI module controls the reception of SCI Data frames automatically and utilizes the
connected DMA channels. A block diagram which presents an overview of the DMA Controlled SCI Data
Frame reception is shown in Figure 26-31. The RX DMA channel is used to transfer the received frame
data into the memory.
When new data was received, the module generates the receive DMA request and the DMA controller
retrieves the provided data from the SCI Data Register (ESCI_DR). The read access from the low byte of
the SCI Data Register (ESCI_DR) signals the end of the DMA cycle for the current data and triggers the
reception of new data. The read access from the SCI Data Register (ESCI_DR) triggers no internal action.
The application request the eSCI module to enter this mode by setting the RXDMA bit in the Control
Register 2 (eSCI_CR2). From this point in time, the module start the generation of DMA requests and
frame transmission and reception. Before entering this mode, the application should perform the following
actions:
1. Configure the module for SCI mode.
2. Enable the receiver by setting RE in Control Register 1 (eSCI_CR1) to 1.
3. Setup the DMA controller channel.
System Memory
DATA 1
DATA 2
DATA N
DMA
Controller
RX DMA
channel
eSCI
26-36
DATA 1
DATA N
SCI Data frame
Figure 26-31. DMA Controlled SCI Data Frame Reception
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor