PXR40RM Datasheet, PDF (1242/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Time Processing Unit (eTPU2)
The TCRCLK filter delay and prescaling determines the minimum detectable TCRCLK pulse widths and,
therefore, its maximum frequency, as shown in Section 29.3.4.4.5, Filter Clock Prescaler and Table 29-19.
The TCRCLK signal delay from the module input to TCR1/TCR2 incrementing or detection in the EAC
logic is explained in the eTPU Reference Manual.
29.3.6 Safety Features
This section describes the Multiple Input Signature Calculator and memory error support features.
The Multiple Input Signature Calculator - MISC - is an SCM test feature accessible through registers
ETPUMCR and ETPUMISCCMPR (see Section 29.2.5, System Configuration Registers). MISC allows
SCM test “on the fly”, i.e., while eTPU is running, with no impact on eTPU functionality or performance.
Memory Error support features comprises SCM and/or SDM error detection, correction, report, and soft
error fix.
29.3.6.1 SCM Test - Multiple Input Signature Calculator
The Multiple Input Signature Calculator (MISC) comprises special hardware that sequentially reads all
SCM positions and calculates, in parallel, a 32-bit signature from a 32-input CRC signature calculator with
the following polynomial:
1 + x¹ + x² + x²² + x³¹
A complete description of the signature calculation procedure can be found in Section 29.4.3, MISC
Algorithm.
Once started by the Host the MISC runs continuously, restarting after the completion of each cycle, when
it sets the ETPUMCR register flag SCMMISC (see Section 29.2.5.1, ETPUMCR - eTPU Module
Configuration Register). The average time for a MISC calculation can be measured by checking
SCMMISC state at regular intervals, incrementing a counter and clearing SCMMISC if it is set.
MISC accesses to the SCM array are executed if none of the engines is accessing the SCM, to avoid
degradation of the microengine performance: it happens while no channel is being serviced. An ongoing
MISC operation can be aborted by writing 0 to SCMMISEN.
The Host must load the register ETPUMISCCMPR (see Section 29.2.5.3, ETPUMISCCMPR - eTPU
MISC Compare Register) with the expected value to be found at the end of the MISC cycle, and then start
the signature calculation writing bit SCMMISEN=1 in register ETPUMCR (see Section 29.2.5.1,
ETPUMCR - eTPU Module Configuration Register). MISC zeroes the signature accumulator and starts
reading SCM data and calculating the signature. After last SCM position is read, MISC compares the value
in signature accumulator against the value in ETPUMISCCMPR: if there is a mismatch MISC stops, a
Global Exception is issued and the bit SCMMISF in register ETPUMCR assumes value 1. If no mismatch
is found, MISC repeats the procedure automatically. When signature is being calculated, SCM address
starts at the last SCM address and counts down to 0. The conditions for executing a MISC operation are
(see also Table 29-16):
• Both microengines in idle state (no channel is being serviced) or stopped, in any combination (e.g.,
engine 1 idle with engine 2 stopped).
• ETPUMCR bit VIS = 0.
29-74
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor