PXR40RM Datasheet, PDF (785/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Modular Input/Output Subsystem (eMIOS200)
Figure 23-41 shows the generated output signal if A1 is set to 0x0. Because the counter does not reach 0
in this mode, the channel internal logic infers a match as if A1 = 0x00_0001 with the difference that in this
case, the positive edge of the match signal is used to trigger the output pin transition instead of the negative
edge used when A1 = 0x00_0001. An A1 positive edge match signal from cycle (n + 1) occurs at the same
time as B1 negative edge match signal from cycle (n). This allows using the A1 positive edge match to
mask the B1 negative edge match when they occur at the same time. The result is that no transition occurs
on the output flip-flop and a 0% duty cycle is generated.
Prescaler Ratio = 2
EDPOL = 0
Write to A2
Cycle n
Cycle n + 1
System Clock
Prescaler
EMIOS_CCNTR
1
A1 Value 0x000004
A2 Value
B1 Value 0x000008
A1 Match
A1 Match Positive Edge Detection
5
4
0x000000
A1 Match
Negative Edge
Detection
1
0x000000
Time
A1 Match Positive Edge Detection
A1 Match Negative Edge Detection
B1 Match
B1 Match Negative Edge Detection
Output Pin
B1 Match Negative Edge Detection
No Transition at this Point
Figure 23-41. OPWFMB Mode with A1 = 0 (0% duty cycle)
Figure 23-42 shows the timing for the A1 and B1 registers load. The A1 and B1 load use the same signal
which is generated at the last system clock period of a counter cycle. Thus, A1 and B1 are updated
respectively with A2 and B2 values at the same time that the EMIOS_CCNTR[n] counter is loaded with
0x00_0001. This event is defined as the cycle boundary. The load signal pulse has the duration of one
system clock period. If A2 and B2 are written within cycle (n), their values are loaded into A1 and B1,
respectively, at the first clock of cycle (n + 1) and the new values are used for matches at cycle (n + 1). The
update disable bits (OU[n] in EMIOS_OUDR) can be used to control the update of these registers, thus
allowing to delay the A1 and B1 registers update for synchronization purposes.
In Figure 23-42, it is assumed that both the channel and global prescalers are set to 0x00_0001 (each divide
ratio is two), meaning that the channel internal counter transitions at every four system clock cycles.
FLAGs can be generated only on B1 matches when MODE[5] is cleared, or on either A1 or B1 matches
when MODE[5] is set. Because the B1 FLAG occurs at the cycle boundary, this flag can be used to indicate
that A2 or B2 data written on cycle (n) were loaded to A1 or B1, respectively, thus generating matches in
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
23-45