PXR40RM Datasheet, PDF (916/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Deserial Serial Peripheral Interface (DSPI)
SCK (CPOL = 0)
SCK (CPOL = 1)
Master SOUT
Master SIN
PCS
t_DT
Figure 25-35. Continuous SCK Timing Diagram (CONT=0)
If the CONT bit in the TX FIFO entry is set or the DCONT in the DSPI_DSICR is set, PCS remains
asserted between the transfers. Under certain conditions, SCK can continue with PCS asserted, but with
no data being shifted out of SOUT (SOUT pulled high). This can cause the slave to receive incorrect data.
Those conditions include:
• Continuous SCK with CONT bit set, but no data in the transmit FIFO.
• Continuous SCK with CONT bit set and entering STOPPED state (refer to Section 25.4.2, Start
and Stop of DSPI Transfers).
• Continuous SCK with CONT bit set and entering Stop mode or Module Disable mode.
Figure 25-36 shows timing diagram for Continuous SCK format with Continuous Selection enabled.
SCK (CPOL = 0)
SCK (CPOL = 1)
Master SOUT
Master SIN
PCS
transfer 1
transfer 2
Figure 25-36. Continuous SCK Timing Diagram (CONT=1)
25.4.9 Timed Serial Bus (TSB)
The DSPI can be programmed in Timed Serial Bus configuration by asserting the TSBC bit in the
DSPI_DSICR register, see Section 25.3.2.10, DSPI DSI Configuration Register (DSPI_DSICR), for
25-56
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor