PXR40RM Datasheet, PDF (304/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Interrupts and Interrupt Controller (INTC)
NOTE:
‘b ISR_n’ is technically
part of the handler.
Address
IVPR + 0x0000
IVPR + 0x0010
IRQ[n]
taken
IVPR + 0x0020
IVPR + n [0x0010]
Refer to definition of N
Instructions
b handler 0
•••
b handler 1
•••
b handler 2
•••
b handler n
•••
b handler N
handler 0
handler n
handler N
Prolog
ISR
Epilog
•••
Prolog
ISR
Epilog
•••
Prolog
ISR
Epilog
Figure 10-4. Program Flow–Hardware Vector Mode
The INTC supports a hardware vector mode that reduces the time between assertion of an interrupt and
execution of the service routine. It also provides 16 priorities so that lower priority ISRs do not delay the
execution of higher priority ISRs. The priority assigned to each interrupt source is programmable in the
range 0 to 15, with 0 being the lowest and 15 being the highest priority.
When multiple tasks share a resource, coherent accesses to that resource need to be supported. The INTC
supports the priority ceiling protocol for coherent accesses. By providing a modifiable priority mask, the
priority level can be raised temporarily so that no task can preempt another task that shares the same
resource.
Multiple processors can assert interrupt requests to each other through software configurable interrupt
requests, i.e., by using application software to assert an interrupt request. These same software
configurable interrupt requests also can be used to break the work involved in servicing an interrupt
request into a high priority portion and a low priority portion. The high priority portion is initiated by a
peripheral interrupt request, but then the ISR can assert a software configurable interrupt request to finish
the servicing in a lower priority ISR.
10.1.3 Features
Features include the following:
• Total number of interrupt vectors is 480, of which:
— 410 are peripheral interrupt vectors
— 8 are software configurable sources
— 62 are reserved sources
• 9-bit unique vector for each interrupt request source in hardware vector mode.
• Each interrupt source can be programmed to one of 16 priorities.
• Preemption.
— Preemptive prioritized interrupt requests to processor.
10-4
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor