PXR40RM Datasheet, PDF (1022/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Queued Analog-to-Digital Converter (EQADC)
Address: 0x0440, 0x0444, 0x0448, 01044C
Access: User read only
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
RFIFO5_DATAw
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 27-32. EQADC RFIFO5 Registers (EQADC_RF0Rw) (w=0, .., 3)
Table 27-19. EQADC_CFxRw Field Descriptions
Field
Description
0–15
Reserved
16–31
RFIFOx Data w (w = 0, .., 3). Reading RFIFOx_DATAw returns the value stored on the w^th entry of
RFIFOx_DATAw RFIFOx. Each RFIFO is composed of four 16-bit entries, with register 0 being mapped to the one with
the smallest memory mapped address.
27.6.3 On-Chip ADC Registers
This section describes a list of registers that control on-chip ADC operation. The ADC registers are not
part of the CPU accessible memory map. These registers can only be accessed indirectly through
configuration commands. There are a set of non-memory mapped registers per ADC, plus a set of registers
shared by both ADCs. The address, usage, and access privilege of each register is shown in Table 27-20.
Data written to or read from reserved areas of the memory map is undefined.
Their assigned addresses are the values used to set the ADC_REG_ADDRESS field of the read/write
configurations commands bound for the on-chip ADCs. These are half-word addresses. Further, the
following restrictions apply when accessing these registers:
• Registers ADC0_CR, ADC0_GCCR, ADC0_OCCR, ADC0_AGR1/2 and ADC0_AOR1/2 can
only be accessed by configuration commands sent to CBuffer0.
• Registers ADC1_CR, ADC1_GCCR, ADC1_OCCR, ADC1_AGR1/2 and ADC1_AOR1/2 can
only be accessed by configuration commands sent to CBuffer1.
• Registers ADC_TSCR, ADC_TBCR, ADC_ACR1-8 and ADC_PUDCR0-7 can be accessed by
configuration commands sent to CBuffer0 or to CBuffer1. A data write to any of these registers
through a configuration command sent to CBuffer0 will write the same memory location as when
writing to it through a configuration command sent to CBuffer1.
NOTE
Simultaneous write accesses from CBuffer0 and CBuffer1 to any of the
shared registers are not allowed.
27-40
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor