PXR40RM Datasheet, PDF (876/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Deserial Serial Peripheral Interface (DSPI)
Field
16–19
CSSCK
20–23
ASC
24–27
DT
28–31
BR
Table 25-7. DSPI_CTARn Field Descriptions (continued)
Descriptions
PCS to SCK Delay Scaler. The CSSCK field selects the scaler value for the PCS to SCK delay. This
field is only used in Master Mode. The PCS to SCK Delay is the delay between the assertion of PCS
and the first edge of the SCK. Table 25-10 list the scaler values.The PCS to SCK Delay is a multiple
of the system clock period and it is computed according to the following equation:
t_CSC
=
-------1--------  PCSSCK  CSSCK
f_periph
See Section 25.4.6.2, PCS to SCK Delay (tCSC), for more details.
Eqn. 25-1
After SCK Delay Scaler. The ASC field selects the scaler value for the After SCK Delay. This field is
only used in Master Mode. The After SCK Delay is the delay between the last edge of SCK and the
negation of PCS. Table 25-11 list the scaler values.The After SCK Delay is a multiple of the system
clock period, and it is computed according to the following equation:
t_ASC
=
-------1--------
f_periph

PASC

ASC
See Section 25.4.6.3, After SCK Delay (tASC), for more details.
Eqn. 25-2
Delay after Transfer Scaler. The DT field selects the Delay after Transfer Scaler. This field is only used
in Master Mode. The Delay after Transfer is the time between the negation of the PCS signal at the
end of a frame and the assertion of PCS at the beginning of the next frame. Table 25-12 lists the scaler
values. In the Continuous Serial Communications Clock operation the DT value is fixed to one TSCK,
except when the TSBC bit from DSPI_DSICR register is enabling the TSB configuration. See detailed
information onSection 25.4.9, Timed Serial Bus (TSB). The Delay after Transfer is a multiple of the
system clock period and it is computed according to the following equation:
t_DT
=
-------1--------
f_periph

PDT

DT
See Section 25.4.6.4, Delay after Transfer (tDT), for more details.
Eqn. 25-3
Baud Rate Scaler. The BR field selects the scaler value for the baud rate. This field is only used in
Master Mode. The prescaled system clock is divided by the Baud Rate Scaler to generate the
frequency of the SCK. Table 25-13 lists the Baud Rate Scaler values.The baud rate is computed
according to the following equation:
SCK baud rate = -^f-^p---^e---^r--ⁱ-^p---^h-  ^{1-----+-----D}-----^B----^R--
PBR BR
See Section 25.4.6.1, Baud Rate Generator, for more details.
Eqn. 25-4
Table 25-8. DSPI SCK Duty Cycle
DBR
0
1
1
1
1
CPHA
any
0
0
0
0
PBR
any
00
01
10
11
SCK Duty Cycle
50/50
50/50
33/66
40/60
43/57
25-16
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor