PXR40RM Datasheet, PDF (979/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Serial Communication Interface (eSCI)
26.4.6.6.1 LIN Wakeup Generation
The eSCI module can cause the LIN bus to exit the sleep mode by sending a break character. The
application triggers the transmission of a break character by writing 1 to the LIN bus wakeup trigger WU
in the LIN Control Register 1 (eSCI_LCR1). After the end of transmission of this break character the
transmitter will neither set the TXRDY flag in the Interrupt Flag and Status Register 2 (eSCI_IFSR2) nor
start the transmission of frame data until the wakeup delimiter period has been expired. The wakeup
delimiter period is defined by the WUD field in the LIN Control Register 1 (eSCI_LCR1).
To generate a valid wakeup character according to LIN 2.0, the eSCI first needs to be programmed to a
baud rate lower than 32 kBaud, then WU can be set. Should the application require a higher baud rate, then
this rate can be set once the wakeup character has been transmitted.
26.4.6.6.2 LIN Wakeup Reception
If the eSCI receives a valid wakeup condition on the selected receiver input the LIN wakeup flag LWAKE
in the Interrupt Flag and Status Register 2 (eSCI_IFSR2) will be set. Since each valid wakeup condition
violates the byte field structure the frame error flag FE in the Interrupt Flag and Status Register 1
(eSCI_IFSR1) will be set too.
The eSCI detects the following conditions as valid wakeup conditions:
• Reception of a break signal
• Reception of a LIN 1.x wakeup character (80h, 00h or C0h)
• Reception of a LIN 2.0 wakeup character (low pulse of 250 ms to 5 ms).
To detect LIN 2.0 wakeup characters, the baud rate must to be set to 32k down to 1.6k baud.
26.4.6.7 LIN Protocol Engine Reset
The LIN protocol engine is reset when the LRES bit in the LIN Control Register 1 (eSCI_LCR1) is set
to 1. In this case, the LIN protocol engine will no longer initiates new transmissions or receptions.
However, ongoing byte transmission or reception is not aborted.
In order to start the LIN Protocol Engine with idle transmitter and receiver processes, the LRES bit should
be asserted for the duration of at least one bit.
26.4.7 Interrupts
This section describes the interrupt sources and interrupt request generation.
26.4.7.1 Interrupt Flags and Enables
All interrupt sources, interrupt flags, and interrupt enable bits are listed in Table 26-36. This table indicates
the operational modes, where the interrupt flags can be set by the eSCI module.
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
26-51