PXR40RM Datasheet, PDF (1276/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

External Bus Interface (EBI)
Table 30-9. EBI_CAL_BR0-3 Descriptions (continued)
Field
Description
20 Port Size
PS The PS bit determines the data bus width of transactions to this chip-select bank.
Note: In the case where the DBM bit in EBI_MCR is set for 16-bit Data Bus Mode, the PS bit value is ignored and
is always treated as a’1’ (16-bit port).
0 32-bit port
1 16-bit port
21–23 Reserved
24 Address on Data Bus Multiplexing
AD_MUX The AD_MUX bit controls whether accesses for this chip select have the address driven on the data bus in the
address phase of a cycle.
0 Address on Data Multiplexing Mode is disabled for this chip select.
1 Address on Data Multiplexing Mode is enabled for this chip select.
25 Burst Length
BL The BL bit determines the amount of data transferred in a burst for this chip select, measured in 32-bit words. The
number of beats in a burst is automatically determined by the EBI to be 4, 8, or 16 according to the Port Size (PS
bit) so that the burst fetches the number of words chosen by BL (see Table 29-10). For internal AMBA data bus width
of 32-bits, the BL bit is ignored (treated as 1).
Value
Burst
Length¹
PS
# Beats in Burst²
0 (32-bit)
8
0³
8-word⁴
1 (16-bit)
16
0 (32-bit)
4
1
4-word
1 (16-bit)
8
1 _{Total amount of data fetched in a burst transfer.}
2 _{Number of external data beats used in external burst transfer. The size of each}
beat is determined by PS value.
3 _{An 8-word burst length is only supported for device’s using 64-bit AMBA data}
bus width to EBI.
4 _{A word always refers to 32-bits of data, regardless of PS.}
Note: The EBI does NOT support a 2-word external burst length. This means that neither a 4-beat burst to a 16-bit
external memory (nor a 2-beat burst to 32-bit external memory) are supported.
26
WEBS
Write Enable / Byte Select
This bit controls the functionality of the D_WE[0:3] signals.
0 The D_WE[0:3] signals function as WE[0:3]
1 The D_WE[0:3] signals function as BE[0:3]
27
TBDIP
Toggle Burst Data in Progress
This bit determines how long the D_BDIP signal is asserted for each data beat in a burst cycle. See
Section 30.4.2.5.1, TBDIP Effect on Burst Transfer, for details.
0 Assert D_BDIP throughout the burst cycle, regardless of wait state configuration.
1 Only assert D_BDIP (BSCY+1) external cycles before expecting subsequent burst data beats.
28 Reserved
30-14
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor