PXR40RM Datasheet, PDF (301/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Chapter 10
Interrupts and Interrupt Controller (INTC)
10.1 Introduction
This chapter describes the interrupt controller (INTC), which schedules interrupt requests (IRQs) from
software and internal peripherals to the e200z7 core. The INTC provides interrupt prioritization and
preemption, interrupt masking, interrupt priority elevation, and protocol support.
Interrupts implemented by the MCU are defined in the e200z7 Core Reference Manual.
10.1.1 Block Diagram
Figure 4-1 shows details of the interrupt controller.
Software
set clear
interrupt
registers
Priority
select
registers
Peripheral
interrupt
requests¹
n¹
Flag bits x 4-bits
8
n¹
Priority
arbitrator
Priority
LIFO
Pushed
4 priority
4
Popped
priority
4
Current
priority
register
End-of-
interrupt
register
Hardware
vector
enable
Module
configuration
1
register
Highest
priority
interrupt
requests
n¹
Request
selector
Lowest
vector
interrupt
request
n¹
1 ^{Vector table}
entry size
Interrupt
Interrupt
Vector
encoder
vector
9
Interrupt
acknowledge
register
vector
9
Highest priority
New
4 priority
Priority
4
comparator
Update interrupt vector 1
Interrupt
request to
processor
1
Current
priority
Interrupt acknowledge 1
Memory-mapped registers
Logic not memory-mapped
Push/update/acknowledge 1
Pop 1
Slave
interface
for reads
and writes
Slave
bus
signals
1 _{Although N (largest addressable IRQ vector number) = 479, this does not indicate the total number of interrupts}
available on this device. The total number of available interrupts on this device is 480: 410 peripheral IRQs,
8 software-configurable IRQs, and 62 reserved.
Figure 10-1. INTC Block Diagram
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
10-1