PXR40RM Datasheet, PDF (1418/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

33.3.5 Cache
Device Performance Optimization
33.3.5.1 Description
The PXR40 provides an 16kB Instruction and 16kB Data, 4-way set-associative, harvard cache design
with a 32-byte line size. The cache is disabled by default when reset is negated.
The cache improves system performance by providing low-latency instructions and data to the e200z7
instruction and data pipelines, which decouples processor performance from system memory performance.
There are several stages to enabling the cache. Not only does the cache itself have to be invalidated then
enabled, but memory regions upon which it can operate must be configured in the MMU to permit cache
access.
33.3.5.2 Recommended configuration
The exact usage of cache is application dependent but some general guidelines for using cache to improve
performance in a typical application are listed below:
• Enable instruction cache for all internal & external memories that code is being executed from.
• Enable data cache for internal data memories that are not shared, unless the application can
guarantee that coherency is maintained between multiple masters.
• Consider locking the stack within the data cache.
• Copyback mode in the cache generally uses fewer system resources. However, write through mode
is better for coherency and to protect for future multi-core devices that require write-thorough
mode be set for inter-core coherency.
• Consider locking critical performance routines in cache.
• Avoid caching memory mapped peripherals for coherency reasons.
The process of enabling the instruction cache involves first invalidating the cache (by setting
L1CSR1[ICINV]) then when invalidation is completed (L1CSR1[ICINV, ICABT]=0) enabling the cache
(by setting L1CSR1[ICE]). A similar process for the data cache using L1CSR0 is required.
The L1CSR1 and L1CSR0 special purpose registers are detailed below. For further details of cache
configuration registers refer to the e200z7 core reference manual.
0
0
0
0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SPR - 1011; Read/Write; Reset - 0x0
Figure 33-2. L1 Cache Control & status Register 1 (L1CSR1)
Table 33-2. L1CSR1 Register Field Descriptions
Field
0–14
15
ICECE
Reserved
Instruction Cache Error Checking Enable
Description
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
33-6