PXR40RM Datasheet, PDF (1328/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Nexus Development Interface (NDI)
Table 31-4. JTAG Client Select Instructions (continued)
JTAGC Instruction
ACCESS_AUX_TAP_MULTI
BYPASS
Opcode
Description
11100 Serialize the JTAG instructions to all internal cores
11111 Bypass the TAP controller
Table 31-5. Nexus Client JTAG Instructions
Instruction
Description
NPC JTAG Instruction Opcodes
NEXUS_ENABLE
Opcode for NPC Nexus Enable instruction (4-bits)
BYPASS
Opcode for the NPC BYPASS instruction (4-bits)
e200z7 OnCE JTAG Instruction Opcodes¹
NEXUS3_ACCESS
Opcode for e200z7 OnCE Nexus Enable instruction (10-bits)
BYPASS
Opcode for the e200z7 OnCE BYPASS instruction (10-bits)
eDMA Nexus JTAG Instruction Opcodes
NEXUS_ACCESS
Opcode for eDMA Nexus Enable instruction (4-bits)
BYPASS
Opcode for the eDMA Nexus BYPASS instruction (4-bits)
FlexRay Nexus JTAG Instruction Opcodes
NEXUS_ACCESS
Opcode for FlexRay Nexus Enable instruction (4-bits)
BYPASS
Opcode for the FlexRay Nexus BYPASS instruction (4-bits)
1 _{See the e200z7 Reference Manual for a complete list of available OnCE instructions.}
Opcode
0x0
0xF
0x7C
0x7F
0x0
0xF
0x0
0xF
31.4.2 Configuring the NDI for Nexus Messaging
The NDI is placed in disabled mode upon exit of power-on reset. If message transmission via the auxiliary
port is desired, a write to the port configuration register (PCR) located in the NPC is then required to enable
the NDI and select the mode of operation. Asserting MCKO_EN in the PCR places the NDI in enabled
mode and enables MCKO. The frequency of MCKO is selected by writing the MCKO_DIV field.
Asserting or negating the FPM bit selects full-port or reduced-port mode, respectively. When writing to
the PCR, the PCR lsb (least significant bit) must be written to a logic 0. Setting the lsb of the PCR enables
factory debug mode and prevents the transmission of Nexus messages.
Table 31-6 describes the NDI configuration options.
Table 31-6. NDI Configuration Options
JCOMP
Asserted
No
Yes
MCKO_EN bit of the Port
Configuration Register
X
0
FPM bit of the Port
Configuration Register
Configuration
X
Reset
X
Disabled
31-12
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor