PXR40RM Datasheet, PDF (1206/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Time Processing Unit (eTPU2)
29.2.9.4 ETPUCDTROSR - eTPU Channel Data Transfer Request Overflow Status
Register
Data Transfer Request Overflow status (see Section 29.3.2.2, Interrupts and Data Transfer Requests) from
all channels are grouped in ETPUCDTROSR. Their bits are mirrored from the Channel Status/Control
registers (see Section 29.2.10.2, ETPUCxSCR - eTPU Channel x Status Control Register) and one must
write 1 to clear a status bit.
eTPU A: Base + 0x230 / eTPU B: Base + 0x234
R
W
RESET:
0
DTR
OS
31
DTR
OC
31
0
1
DTR
OS
30
DTR
OC
30
0
2
DTR
OS
29
DTR
OC
29
0
3
DTR
OS
28
DTR
OC
28
0
4
DTR
OS
27
DTR
OC
27
0
5
DTR
OS
26
DTR
OC
26
0
6
DTR
OS
25
DTR
OC
25
0
7
DTR
OS
24
DTR
OC
24
0
8
DTR
OS
23
DTR
OC
23
0
9
DTR
OS
22
DTR
OC
22
0
10
DTR
OS
21
DTR
OC
21
0
11
DTR
OS
20
DTR
OC
20
0
12
DTR
OS
19
DTR
OC
19
0
13
DTR
OS
18
DTR
OC
18
0
14
DTR
OS
17
DTR
OC
17
0
15
DTR
OS
16
DTR
OC
16
0
R
W
RESET:
16
DTR
OS
15
DTR
OC
15
0
17
DTR
OS
14
DTR
OC
14
0
18
DTR
OS
13
DTR
OC
13
0
19
DTR
OS
12
DTR
OC
12
0
20
DTR
OS
11
DTR
OC
11
0
21
DTR
OS
10
DTR
OC
10
0
22
DTR
OS
9
DTR
OC
9
0
23
DTR
OS
8
DTR
OC
8
0
24
DTR
OS
7
DTR
OC
7
0
25
DTR
OS
6
DTR
OC
6
0
26
DTR
OS
5
DTR
OC
5
0
27
DTR
OS
4
DTR
OC
4
0
28
DTR
OS
3
DTR
OC
3
0
29
DTR
OS
2
DTR
OC
2
0
30
DTR
OS
1
DTR
OC
1
0
31
DTR
OS
0
DTR
OC
0
0
Figure 29-18. ETPUCDTROSR Register
DTROSx — Channel x Data Transfer Request Overflow Status
1 = indicates that data transfer request overflow occurred in the channel.
0 = indicates that no data transfer request overflow occurred in the channel.
DTROCx — Channel x Data Transfer Request Overflow Clear
1 = clear status bit.
0 = keep status bit unaltered.
For details about data transfer request overflow, see Section 29.3.2.2.2, Interrupt and Data Transfer
Request Overflow.
29-38
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor