PXR40RM Datasheet, PDF (204/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

System Integration Unit (SIU)
7.3.1.11 IRQ Digital Filter Register (SIU_IDFR)
The SIU_IDFR specifies the amount of digital filtering on IRQ[0]–IRQ[15]. The digital filter length field
specifies the number of system clocks that define the period of the digital filter and the minimum time an
IRQ signal must hold the active state to qualify as an edge-triggered event.
Address: SIU_BASE + 0x0030
Access: R/W
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
R0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R0
0
0
0
0
0
0
0
0
0
0
0
DFL
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 7-12. IRQ Digital Filter Register (SIU_IDFR)
The following table describes the field in the IRQ digital filter register:
Table 7-18. SIU_IDFR Bit Field Descriptions
Field
Function
0–27
28–31
DFL
Reserved
Digital filter length. Defines the digital filter period on the IRQ[n] inputs according to the following equation:
Filter Period = SystemClockPeriod  2DFL + 1S ystemClockPeriod 
For a 100 MHz system clock, this gives a range of 20 ns to 328 µs. The minimum time of three clocks accounts for
synchronization of the IRQ input pins with the system clock.
7.3.1.12 IRQ Filtered Input Register (SIU_IFIR)
The SIU_IFIR is a read only register where the filtered values of the NMI and IRQ[0]–IRQ[15] pins are
captured.
7-22
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor