PXR40RM Datasheet, PDF (864/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Deserial Serial Peripheral Interface (DSPI)
DSPI_C clock and data signals are available on LVDS pairs to support microsecond bus functionality.
Table 25-1 is an example of the options for PA on two balls, where “true” and “complement” LVDS
outputs are multiplexed with SCKC and SINC.
Table 25-1. LVDS Example
PCR235¹[PA] PCR236²[PA]
Selection Selection
SCKC Ball
function
SINC Ball
function
SCKC
SINC
SCKC
SINC
LVDS
SCKC
LVDS
LVDS
SCK_C_LVDS+ SCK_C_LVDS–
SCKC
undriven
LVDS
SINC
NOTES:
1 _{SCKC_SCK_C_LVDSP_GPIO235}
2 _{SINC_SCK_C_LVDSM_GPIO236}
undriven
SINC
Signals lvds_opt0 and lvds_opt1 control the voltage swing on the LVDS pad. These two signals are
controlled by bits SRC[0:1] of the respective PCR register. Table 25-2 gives the configuration for these
bits.
Table 25-2. LVDS Pads Voltage Swing
SRC[0]
0
0
1
1
SRC[1]
0
1
0
1
Current flowing in
the driver
normal
decreased
increased
normal
Differential Voltage across
pad_p and pad_n
default
decreased
increased
same as default
25.1.3 DSPI Configurations
The DSPI block has three distinct serial transmission configurations: SPI, DSI and CSI.
25.1.3.1 SPI Configuration
The SPI Configuration allows the DSPI to send and receive serial data. This configuration allows the DSPI
to operate as a basic SPI block with the FIFOs providing support for external queue operation. Data to be
transmitted and data received reside in separate FIFOs. The FIFOs can be popped and pushed by host
software or by a DMA controller.
25.1.3.2 DSI Configuration
In the DSI Configuration the DSPI serializes up to 16 Parallel Input signals or register bits. The DSPI also
deserializes the received data to Parallel Output signals or to a memory-mapped register. The data is
transferred using a SPI-like protocol.
25-4
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor