PXR40RM Datasheet, PDF (719/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

FlexRay Communication Controller (FLEXRAY)
After reading all the data from the locked tables, the application must unlock the table by writing to the
even table lock trigger SFTCCSR.ELKT again. The even table lock status bit SFTCCSR.ELKS is reset
immediately.
If the sync frame table generation is disabled, the table valid bits SFTCCSR[EVAL] and
SFTCCSR[EVAL] are reset when the counter values in the Sync Frame Counter Register (SFCNTR) are
updated. This is done because the tables stored in the flexray memory are no longer related to the values
in the Sync Frame Counter Register (SFCNTR).
SFTCCSR.[OPT,SIDEN,SDVEN] write window
even table write
odd table write
static segment
cycle 2n-1
NIT
static segment
cycle 2n
NIT
static segment
NIT
cycle 2n+1
Figure 22-145. Sync Frame Table Trigger and Generation Timing
22.6.12.5 Sync Frame Table Access
The sync frame tables will be transferred into the flexray memory during the table write windows shown
in Figure 22-145. During the table write, the application can not lock the table that is currently written. If
the application locks the table outside of the table write window, the lock is granted immediately.
22.6.12.5.1 Sync Frame Table Locking and Unlocking
The application locks the even/odd sync frame table by writing 1 to the lock trigger bit ELKT/OLKT in
the Sync Frame Table Configuration, Control, Status Register (SFTCCSR). If the affected table is not
currently written to the flexray memory, the lock is granted immediately, and the lock status bit
ELKS/OLKS is set. If the affected table is currently written to the flexray memory, the lock is not granted.
In this case, the application must issue the lock request again until the lock is granted.
The application unlocks the even/odd sync frame table by writing 1 to the lock trigger bit ELKT/OLKT.
The lock status bit ELKS/OLKS is cleared immediately.
22.6.13 MTS Generation
The controller provides a flexible means to request the transmission of the Media Access Test Symbol
MTS in the symbol window on channel A or channel B.
The application can configure the set of communication cycles in which the MTS will be transmitted over
the FlexRay bus by programming the CYCCNTMSK and CYCCNTVAL fields in the MTS A
Configuration Register (MTSACFR) and MTS B Configuration Register (MTSBCFR).
The application enables or disables the generation of the MTS on either channel by setting or clearing the
MTE control bit in the MTS A Configuration Register (MTSACFR) or MTS B Configuration Register
(MTSBCFR). If an MTS is to be transmitted in a certain communication cycle, the application must set
the MTE control bit during the static segment of the preceding communication cycle.
The MTS is transmitted over channel A in the communication cycle with number CYCCNT, if
Equation 22-20, Equation 22-21, and Equation 22-21 are fulfilled.
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
22-135