PXR40RM Datasheet, PDF (161/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Frequency Modulated Phase-Locked Loop (FMPLL)
— Register programmable modulation rates of F_extal/80, F_extal/40, and F_extal/20 (modulation rate
must be between 400 kHz and 1 MHz).
• Lock detect circuitry provides a signal indicating the FMPLL has acquired lock and continuously
monitors the FMPLL output for any loss of lock
• Loss-of-clock circuitry monitors input reference and FMPLL output clocks with programmable
ability to select a backup clock source as well as generate a reset or interrupt in the event of a failure
6.1.3 Modes of Operation
There are two main modes of FMPLL: PLL Off mode and normal mode. These modes are briefly
described in this section.
When PLL Off mode is selected, the FMPLL is turned off; the clock source must come from somewhere
else or the device will not function. The lock detector is not functional and does not indicate that the
FMPLL is in a locked state. Frequency modulation is not available and the FMPLL is put into a low-power,
idle state. A full swing square wave clock input for the entire system must be supplied on the EXTAL pin
(Refer to PXR40 Microcontroller Data Sheet for external clock input requirements). This operating mode
is described in Section 6.4.2, PLL Off Mode.
When normal mode is selected, the FMPLL is fully programmable. The FMPLL reference clock source
can be a crystal oscillator or an external clock generator. The lock detector indicates the lock status of the
FMPLL, and frequency modulation of the output clock can be enabled. This operating mode is described
in Section 6.4.3, Normal Mode.
6.2 External Signal Description
Refer to Chapter 3, Signal Descriptions, for detailed signal descriptions.
6.3 Memory Map and Registers
This section provides a detailed description of the FMPLL registers.
6.3.1 Module Memory Map
Table 6-1 shows the FMPLL memory map. The address of each register is given as an offset to the FMPLL
base address. The table lists registers in the order of their addresses, identified by complete name and
mnemonic, and the type of their accesses.
Table 6-1. FMPLL Memory Map
Offset from
FMPLL_BASE_ADDR
(0xC3F8_0000)
Register
0x0000
0x0004
Reserved
SYNSR—FMPLL synthesizer status register
Bits Access Reset Value
32 R/W
—¹
Section/Page
6.3.2.1/6-4
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor
6-3