PXR40RM Datasheet, PDF (1013/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Queued Analog-to-Digital Converter (EQADC)
Address: 0x00A0
0
1
2
3
4
5
6
7
8
9 10 11
R CFS0_TCB0 CFS1_TCB0 CFS2_TCB0 CFS3_TCB0 CFS4_TCB0 CFS5_TCB0
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
Access: User read/write
12 13 14 15
0
0
0
0
0
0
0
0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R0
LCFTCB0
TC_LCFTCB0
W
Reset 0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
Figure 27-15. EQADC CFIFO Status Snapshot Register 0 (EQADC_CFSSR0)
Address: 0x00A4
0
1
2
3
4
5
6
7
8
9 10 11
R CFS0_TCB1 CFS1_TCB1 CFS2_TCB1 CFS3_TCB1 CFS4_TCB1 CFS5_TCB1
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
Access: User read/write
12 13 14 15
0
0
0
0
0
0
0
0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R0
LCFTCB1
TC_LCFTCB1
W
Reset 0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
Figure 27-16. EQADC CFIFO Status Snapshot Register 1 (EQADC_CFSSR1)
Table 27-14. EQADC_CFSSRx Field Descriptions
Field
Description
0–11
CFSx_TCBn
12–16
CFIFO Status at Transfer to CBuffern (n=0,1). CFSx_TCBn indicates the CFIFOx status of previously
completed command transfer. CFSx_TCBn is a copy of the corresponding CFSx in the Section 27.6.2.10,
EQADC CFIFO Status Register (EQADC_CFSR), captured at the time a current command transfer to
CBuffern is initiated.
Reserved
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
27-31