PXR40RM Datasheet, PDF (1186/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Time Processing Unit (eTPU2)
Table 29-5. Detailed Memory Map eTPU A/B (continued)
Offset
0x290
0x294
0x298–0x3FF
0x400
0x404
0x408
0x40C
0x410
0x414
0x418
0x41C
0x5F0
0x5F4
0x5F8
0x5FC - 0x7FF
0x800
0x804
0x808
0x80C
0x810
0x814
0x818
0x81C
0x9F0
Register
ETPUCSSR_A—eTPU A Channel Service
Status Register
ETPUCSSR_B—eTPU B Channel Service
Status Register
Reserved
ETPUC0CR_A—eTPU A Channel 0
Configuration Register
ETPUC0SCR_A—eTPU A Channel 0 Status
and Control Register
ETPUC0HSRR_A—eTPU A Channel 0 Host
Service Request Register
Reserved
ETPUC1CR_A—eTPU A Channel 1
Configuration Register
ETPUC1SCR_A—eTPU A Channel 1 Status
and Control Register
ETPUC1HSRR_A—eTPU A Channel 1 Host
Service Request Register
Reserved
.
.
ETPUC31CR_A—eTPU A Channel 31
Configuration Register
ETPUC31SCR_A—eTPU A Channel 31 Status
and Control Register
ETPUC31HSRR_A—eTPU A Channel 31 Host
Service Request Register
Reserved
ETPUC0CR_B—eTPU B Channel 0
Configuration Register
ETPUC0SCR_B—eTPU B Channel 0 Status
and Control Register
ETPUC0HSRR_B—eTPU B Channel 0 Host
Service Request Register
Reserved
ETPUC1CR_B—eTPU B Channel 1
Configuration Register
ETPUC1SCR_B—eTPU B Channel 1 Status
and Control Register
ETPUC1HSRR_B—eTPU B Channel 1 Host
Service Request Register
Reserved
.
.
.
ETPUC31CR_B—eTPU B Channel 31
Configuration Register
Bits Access Reset Value
32
R
0x0000_0000
32
R
0x0000_0000
32
R/W 0x0000_0000
32
R/W 0x0000_0000
32
R/W 0x0000_0000
32
R/W 0x0000_0000
32
R/W 0x0000_0000
32
R/W 0x0000_0000
32
R/W 0x0000_0000
32
R/W 0x0000_0000
32
R/W 0x0000_0000
32
R/W 0x0000_0000
32
R/W 0x0000_0000
32
R/W 0x0000_0000
32
R/W 0x0000_0000
32
R/W 0x0000_0000
32
R/W 0x0000_0000
32
R/W 0x0000_0000
Section/Page
29.2.9.8/29-41
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29-18
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor