PXR40RM Datasheet, PDF (690/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

FlexRay Communication Controller (FLEXRAY)
Message Buffer Header Field: Data Field Offset
CFG
Message Buffer Header Field: Frame Header
Message Buffer Header Field: Slot Status
RX
MSG
Message Buffer Data Field: DATA[0-N]
MBIDXRn[MBIDX]
MBCCSRn[DVAL/DUP]
MBCCSRn[MTD]
MBCCFRn[CHA/CHB/CCF*]
SR
MBFIDRn[FID]
Figure 22-127. Receive Message Buffer Access Regions
Table 22-100. Receive Message Buffer Access Region Description
Region
Access from
Application
Module
Region used for
CFG
MSG
RX
SR
read/write
read/write
-
-
-
-
write-only
read-only
Message Buffer Configuration, Message Data and Status Access
Message Data, Header, and Status Access
Message Reception and Status Update
Message Buffer Search Data
The trigger bits MBCCSRn[EDT] and MBCCSRn[LCKT] and the interrupt enable bit MBCCSRn[MBIE]
are not under access control and can be accessed from the application at any time. The status bits
MBCCSRn[EDS] and MBCCSRn[LCKS] are not under access control and can be accessed from the
controller at any time.
The interrupt flag MBCCSRn[MBIF] is not under access control and can be accessed from the application
and the controller at any time. controller set access has higher priority.
The controller restricts its access to the regions depending on the current state of the message buffer. The
application must adhere to these restrictions in order to ensure data consistency. The receive message
buffer states are given in Figure 22-128. A description of the message buffer states is given in Table 22-96,
which also provides the access scheme for the access regions.
The status bits MBCCSRn[EDS] and MBCCSRn[LCKS] provide the application with the required status
information. The internal status information is not visible to the application.
22-106
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor