PXR40RM Datasheet, PDF (752/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Modular Input/Output Subsystem (eMIOS200)
Table 23-7. EMIOS_CADR[n], EMIOS_CBDR[n], and EMIOS_ALTA[n] Values Assignment (continued)
Operation Mode
Write
Read
Register Access
Write Read Alternate Write Alternate Read
OPWFMB
A2
A1
B2
B1
—
—
OPWMCB
A2
A1
B2
B1
—
—
OPWMB
A2
A1
B2
B1
—
—
1 _{In these modes, the register EMIOS_CBDR[n] is not used, but B2 can be accessed.}
23.3.2.6 eMIOS200 Counter Register (EMIOS_CCNTR[n])
Offset: UC[n] base address + 0x0008
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R0
0
0
0
0
0
0
0
C[0:23]
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
C[0:23]
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1 _{In GPIO mode or freeze action, this register is writable.}
Figure 23-7. eMIOS200 Counter Register (EMIOS_CCNTR[n])
The EMIOS_CCNTR[n] register contains the value of the internal counter for eMIOS channel n. When
GPIO mode is selected or the channel is frozen, the EMIOS_CCNTR[n] register is read/write. For all other
modes, the EMIOS_CCNTR[n] is a read-only register. When entering some operation modes, this register
is automatically cleared (refer to Section 23.4.1.1, Unified Channel Modes of Operation, for details).
Depending on the channel configuration it may have an internal counter or not. It means that if at least one
mode that requires the counter is implemented, then the counter is present, otherwise it is absent.
23.3.2.7 eMIOS200 Control Register (EMIOS_CCR[n])
Offset: UC[n] base address + 0x000C
Access: User read/write
0
1
R
FREN ODIS
W
Reset 0
0
2
3
ODISSL
0
0
4
5
6
7
8
UCPRE
UC
PREN
DMA
0
0
0
0
0
0
9
10
11
12
13
14
15
0
IF
FCK FEN
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R0
W
0 _{FORC FORC} 0
MA MB
BSL
ED ED
SEL POL
MODE
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 23-8. eMIOS200 Control Register (EMIOS_CCR[n])
23-12
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor