PXR40RM Datasheet, PDF (786/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Modular Input/Output Subsystem (eMIOS200)
cycle (n + 1). Note that the FLAG has a synchronous operation, meaning that it is asserted one system
clock cycle after the FLAG set event.
MODE[6] = 1
EDPOL = 0
Prescaler Ratio = 4
Internal Counter
Cycle n
Write to A2
Match A1
Cycle (n + 1)
Cycle (n + 2)
Match A1
Write to B2
Match B1
Match B1
Write to A2
Match B1
0x000008
0x000006
0x000004
0x000002
0x000001
Due to B1 Match
Cycle (n – 1)
Output Pin
FLAG Set Event
FLAG Pin/Register
FLAG Clear
Time
A1/B1 Load Signal
A1 Value
A2 Value
B1 Value
B2 Value
0x000002
0x000004
0x000006
0x000002 0x000004
0x000006
0x000008
0x000006
0x000008
0x000006
Figure 23-42. OPWFMB A1 and B1 Registers Update and Flags
Figure 23-43 shows the operation of the output disable feature in OPWFMB mode. In contrast to the
OPWFM mode, the output disable forces the channel output flip-flop to the value of the EDPOL bit. This
functionality targets applications that use active-high signals and a high-to-low transition at A1 match. In
this case, EDPOL should be set to 0. Note that both the channel and global prescalers are set to 0x00_0000
(each divide ratio is one), meaning that the channel internal counter transitions at every system clock cycle.
23-46
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor