PXR40RM Datasheet, PDF (1165/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Decimation Filter
The ALT_CONFIG_SEL field should be set to select the ADC_ACRn register that was configured in
Section 28.5.2.1.3. For example, if ADC_ACR1 were selected, then the ALT_CONFIG_SEL field should
be 0x08.
28.5.2.2 Use Case 2 - Input/Output from/to the CPU/DMA, Stored data filtering.
The input to Filter C is through the memory mapped input register.
Filter C is configured as a 4th order low pass IIR.
The output from the filter is routed to a memory mapped output register and an interrupt is issued when
new data is available.
In this example the ADC is not used at all, and no ADC configuration or commands are needed to support
the Decimation Filter operation.
Decimation is not enabled.
Saturation is enabled.
28.5.2.2.1 DECFILT_C_MCR — Module Configuration Register settings
Enable interrupt when new filtered data is available: ODEN=1
Enable IIR Filter type: FTYPE=1
Scale coefficients to a range of +1 to -1: SCAL=8
Enable saturation of filter output result: SAT=1
Select the CPU/DMA as the output destination to transfer data to memory mapped output register:
DECFILT_x_MCR[IO_SEL[0:1] = 01 or 10
Select no decimation: DEC_RATE=0
28.5.2.2.2 DECFILT_C_COEFn
Write the filter coefficients given in Table 28-20 to the following registers.
DECFILT_C_COEF0 = 0x005AB5
DECFILT_C_COEF1 = 0x001240
DECFILT_C_COEF2 = 0x008277
DECFILT_C_COEF3 = 0x001240
DECFILT_C_COEF4 = 0x005AB5
DECFILT_C_COEF5 = 0x2B29E6
DECFILT_C_COEF6 = 0xCC414E
DECFILT_C_COEF7 = 0x1EB97D
DECFILT_C_COEF8 = 0xF8546A
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
28-51