PXR40RM Datasheet, PDF (893/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Deserial Serial Peripheral Interface (DSPI)
25.4.1 Modes of Operation
The DSPI has these distinct modes:
• Master Mode
• Slave Mode
• Module Disable Mode
• External Stop Mode
• Debug Mode
Master, Slave, and Module Disable Modes are block-specific modes while External Stop and Debug
Modes are MCU-specific modes.
The block-specific modes are determined by bits in the DSPI_MCR register. External Stop Mode and
Debug Mode are modes that the entire MCU can enter in parallel with the DSPI being configured in one
of its block-specific modes.
25.4.1.1 Master Mode
In Master Mode the DSPI can initiate communications with peripheral devices. The DSPI operates as bus
master when the MSTR bit in the DSPI_MCR register is set. The Serial Communications Clock (SCK) is
controlled by the Master DSPI. All three DSPI configurations are valid in Master Mode.
In SPI Configuration, Master Mode transfer attributes are controlled by the SPI command in the current
TX FIFO entry. The CTAS field in the SPI command selects which of the eight DSPI_CTAR registers will
be used to set the transfer attributes. Transfer attribute control is on a frame by frame basis. See
Section 25.4.3, Serial Peripheral Interface (SPI) Configuration, for more details.
In DSI Configuration, Master Mode transfer attributes are controlled by the DSPI DSI Configuration
Register (DSPI_DSICR). The DSISCTAS field in the DSPI_DSICR selects which of the DSPI_CTAR
registers will be used to set the transfer attributes. Transfer attributes are set up during initialization and
should not be changed between frames. See Section 25.4.4, Deserial Serial Interface (DSI) Configuration,
for more details.
In CSI Configuration, the DSI data is transferred using DSI Configuration transfer attributes and SPI data
is transferred using the SPI Configuration transfer attributes. In order for the bus slave to distinguish
between DSI and SPI frames, the transfer attributes for the two types of frames must utilize different
Peripheral Chip Select signals. See Section 25.4.5, Combined Serial Interface (CSI) Configuration, for
details.
25.4.1.2 Slave Mode
In Slave Mode the DSPI responds to transfers initiated by a SPI master. The DSPI operates as bus slave
when the MSTR bit in the DSPI_MCR is negated. The DSPI slave is selected by a bus master by having
the slave’s SS asserted. In Slave Mode the SCK is provided by the bus master. All transfer attributes are
controlled by the bus master but clock polarity, clock phase and numbers of bits to transfer must still be
configured in the DSPI slave for proper communications.
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
25-33