PXR40RM Datasheet, PDF (1419/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Field
16
ICEI
17
18–19
ICEDT
20
21
ICUL
22
ICLO
23
ICLFC
24
ICLOA
25–26
ICEA
27–28
29
ICABT
30
ICINV
31
ICE
Device Performance Optimization
Table 33-2. L1CSR1 Register Field Descriptions (continued)
Instruction Cache Error Injection Enable
Description
Reserved
Instruction Cache Error Detection Type
Reserved
Instruction Cache Unable to Lock
Instruction Cache Lock Overflow
Instruction Cache Lock Bits Flash Clear
Instruction Cache Lock Overflow Allocate
Instruction Cache Error Action
Reserved
Instruction Cache Operation Aborted
Indicates a Cache Invalidate or a Cache Lock Bits Flash Clear operation was aborted prior to completion. This
bit is set by hardware on an aborted condition, and will remain set until cleared by software writing 0 to this bit
location.
Instruction Cache Invalidate
0 - No cache invalidate
1 - Cache invalidation operation
When written to a ‘1’, a cache invalidation operation is initiated by hardware. Once complete, this bit is reset to
‘0’. Writing a ‘1’ while an invalidation operation is in progress will result in an undefined operation. Writing a ‘0’ to
this bit while an invalidation operation is in progress will be ignored. Cache invalidation operations require
approximately 36 cycles to complete. Invalidation occurs regardless of the enable (ICE) value.
During cache invalidations, the parity check bits are written with a value dependent on the ICEDT selection.
ICEDT should be written with the desired value for subsequent cache operation when ICINV is set to ‘1’ for proper
operation of the cache.
Instruction Cache Enable
0 - Cache is disabled
1 - Cache is enabled
When disabled, cache lookups are not performed for instruction accesses.
Other L1CSR0 cache control operations are still available.
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
33-7