PXR40RM Datasheet, PDF (419/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Core (e200z7) Overview
13.9.4 Instruction Storage Interrupt (IVOR3)
An Instruction Storage interrupt (ISI) occurs when no higher priority exception exists and an Execute
Access Control exception occurs.
Interrupt Type
Instruction Storage
Table 13-19. ISI Exceptions and Conditions
Interrupt Vector
Offset
Register
IVOR 3
Causing Conditions
1. Access control.
2. Byte ordering due to misaligned instruction across page boundary to
pages with mismatched VLE bits, or access to page with VLE set, and E
indicating little-endian.
3. Misaligned Instruction fetch due to a change of flow to an odd halfword
instruction boundary on a BookE (non-VLE) instruction page.
Table below lists register settings when an ISI is taken.
Table 13-20. Instruction Storage Interrupt—Register Settings
Register
Setting Description
SRR0
SRR1
MSR
ESR
MCSR
DEAR
Vector
Set to the effective address of the excepting instruction.
Set to the contents of the MSR at the time of the interrupt
UCLE 0
SPE 0
WE 0
CE —
EE 0
PR 0
FP 0
ME —
FE0 0
DE —
[BO, MIF, VLEMI]. All other bits cleared.
Unchanged
Unchanged
IVPR_0:15 || IVOR3_16:27 || 4b0000
FE1 0
IS 0
DS 0
PMM 0
RI —
13.9.5 External Input Interrupt (IVOR4)
An External Input exception is signalled to the processor by the assertion an interrupt from the interrupt
controller. The input is a level-sensitive signal expected to remain asserted until core acknowledges the
external interrupt. If input is negated early, recognition of the interrupt request is not guaranteed. When the
core detects the exception, if the exception is enabled by MSR_EE, it takes the External Input interrupt.
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
13-31