PXR40RM Datasheet, PDF (799/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Modular Input/Output Subsystem (eMIOS200)
• Any value written to A2 or B2 on cycle(n) is loaded to A1 and B1 registers at the following cycle
boundary (assuming (OU[n] in EMIOS_OUDR) is not asserted). The new values are used for A1
and B1 matches in cycle(n + 1)
Figure 23-53 shows the operation of the OPWMB mode regarding A1 and B1 matches and the transition
of the channel output pin. In this example, EDPOL is set to 0.
EDPOL = 0
Cycle n
Write to A2
Cycle (n + 1)
Clock
Prescaler
Selected
Counter Bus
1
A1 Value 0x000004
A2 Value
B1 Value 0x000006
A1 Match
A1 Match Positive
Edge Detection
A1 Match Negative
Edge Detection
B1 Match
B1 Match Negative
Edge Detection
4
0x000000
6
6
1
0x000000
A1 Match Negative Edge
Detection
A1 Match Positive Edge Detection
B1 Match Negative Edge
Detection
8
Time
Output Pin
FLAG Bit Set
Figure 23-53. OPWMB Mode Matches and Flags
The output pin transitions are based on the negative edges of the A1 and B1 match signals. Figure 23-53
shows in cycle(n + 1) the value of the A1 register being set to 0. In this case, the match positive edge is
used instead of the negative edge to transition the output flip-flop.
Figure 23-54 shows the channel operation for 0% duty cycle. Note that the A1 match positive edge signal
occurs at the same time as the B1 = 0x00_0008 negative edge signal. In this case A1 match has precedence
over B1 match, causing the output pin to remain at EDPOL bit value, thus generating a 0% duty cycle
signal.
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
23-59