PXR40RM Datasheet, PDF (1214/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Time Processing Unit (eTPU2)
1 = clear status bit.
0 = keep status bit unaltered
These bits are mirrored in ETPUCISR - see Section 29.2.9.2, ETPUCDTRSR - eTPU Channel Data
Transfer Request Status Register). See also the eTPU Reference Manual for details.
DTROS — Data Transfer Request Overflow Status
1 = data transfer request overflow asserted for this channel
0 = data transfer request overflow negated for this channel
DTROC — Data Transfer Request Overflow Clear
1 = clear status bit.
0 = keep status bit unaltered.
These bits are mirrored in ETPUCDTROSR - see Section 29.2.9.4, ETPUCDTROSR - eTPU Channel
Data Transfer Request Overflow Status Register). See also Section 29.3.2.2.2, Interrupt and Data
Transfer Request Overflow.
IPS — Channel Input Pin State
This bit shows the current value of the filtered channel input signal state
OPS — Channel Output Pin State
This bit shows the current value driven in the channel output signal, including the effect of the external
output disable feature (see Section 29.2.2.4, eTPU Channel Output Disable Signals). If the channel
input and output signals are connected to the same pad, OPS reflects the value driven to the pad (if
OBE=1). This is not necessarily the actual pad value, which drives the value in the bit IPS.
OBE — Output Buffer Enable
This bit shows the state of the channel output buffer enable signal, controlled by microcode.
FM[0:1] — Channel Function Mode¹
Each function uses this field for specific configuration. These bits can be tested by microengine code
(see the eTPU Reference Manual for details).
1. These bits are equivalent to the TPU/TPU2/TPU3 Host Sequence (HSQ) bits.
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PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor