PXR40RM Datasheet, PDF (588/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

FlexRay Communication Controller (FLEXRAY)
NOTE
The controller does not provide a memory protection scheme for the flexray
memory.
22.1.5 Features
The controller provides the following features:
• FlexRay Communications System Protocol Specification, Version 2.1 Rev A compliant protocol
implementation
• FlexRay Communications System Electrical Physical Layer Specification, Version 2.1 Rev A
compliant bus driver interface
• single channel support
— FlexRay Port A can be configured to be connected either to physical FlexRay channel A or
physical FlexRay channel B.
• FlexRay bus data rates of 10 Mbit/s, 8 Mbit/s, 5 Mbit/s, and 2.5 Mbit/s supported
• 128 configurable message buffers with
— individual frame ID filtering
— individual channel ID filtering
— individual cycle counter filtering
• message buffer header, status and payload data stored in dedicated flexray memory
— allows for flexible and efficient message buffer implementation
— consistent data access ensured by means of buffer locking scheme
— application can lock multiple buffers at the same time
• size of message buffer payload data section configurable from 0 up to 254 bytes
• two independent message buffer segments with configurable size of payload data section
— each segment can contain message buffers assigned to the static segment and message buffers
assigned to the dynamic segment at the same time
• zero padding for transmit message buffers in static segment
— applied when the frame payload length exceeds the size of the message buffer data section
• transmit message buffers configurable with state/event semantics
• message buffers can be configured as
— receive message buffer
— single buffered transmit message buffer
— double buffered transmit message buffer (combines two single buffered message buffer)
• individual message buffer reconfiguration supported
— means provided to safely disable individual message buffers
— disabled message buffers can be reconfigured
• two independent receive FIFOs
— one receive FIFO per channel
— up to 255 entries for each FIFO
22-4
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor