PXR40RM Datasheet, PDF (400/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Core (e200z7) Overview
13.4.1 Overview
The PXR40 Memory Management Unit is a 32-bit PowerPC Book E compliant implementation, with the
following feature set:
• Translates from 32-bit effective to 32-bit real addresses
• 64-entry fully associative TLB with support for twenty-three page sizes (1K, 2K, 4K, 8K, 16K,
32K, 64K, 128K, 256K, 512K, 1M, 2M, 4M, 8M, 16M, 32M, 64M, 128M, 256M, 512M, 1G, 2G,
4G)
• Hardware assist for TLB miss exceptions
• Software managed by tlbre, tlbwe, tlbsx, tlbsync, and tlbivax instructions
13.4.2 MMU Instructions
13.4.3 TLB Read Entry Instruction (tlbre)
The TLB read entry instruction causes the content of a single TLB entry to be placed in the MMU assist
registers. The entry is specified by the TLBSEL and ESEL fields of the MAS0 register. The entry contents
are placed in the MAS1, MAS2, and MAS3 registers.
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PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor