PXR40RM Datasheet, PDF (959/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Serial Communication Interface (eSCI)
26.4.5.2.4 DMA Controlled SCI Data Frame Transmission
In this mode, the eSCI module handles the generation of Data Frames internally.
When new data required for transmission, the module generates the transmit DMA request and the DMA
controller delivers the required data via write accesses to SCI Data Register (ESCI_DR). The write access
to the low byte of SCI Data Register (ESCI_DR) triggers the transmission of the data. The write access to
the high byte of SCI Data Register (ESCI_DR) triggers no internal operation.
The application request the eSCI module to enter this mode by setting the TXDMA bit in the Control
Register 2 (eSCI_CR2). From this point in time, the module start the generation of DMA requests and
frame transmission. Before entering this mode, the application should perform the following actions:
1. Configure the module for SCI mode.
2. Enable the transmitter by setting TE in Control Register 1 (eSCI_CR1) to 1.
3. Setup the DMA controller channel and provide frame data in system memory
A block diagram which presents an overview of the DMA Controlled Date Frame Transmission is shown
in Figure 26-26.
System Memory
DATA 1
DATA 2
DMA
Controller
TX DMA
channel
eSCI
DATA N
DATA 1
DATA N
SCI Data frame
Figure 26-26. DMA Controlled SCI Data Frame generation
26.4.5.2.5 Parity Generation
The eSCI module generates the parity bit in transmitted data frame when the parity enable bit PE in the
Control Register 1 (eSCI_CR1) is set. The parity type bit PT in the Control Register 1 (eSCI_CR1) defines
whether the odd or even parity is generated.
26.4.5.2.6 Preamble Transmission
The transmission of a preamble is started when the transmitter is in Ready state, the internal iPRE bit,
which is not visible to the application, is set, and the SBK in the Control Register 1 (eSCI_CR1) is clear.
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
26-31