PXR40RM Datasheet, PDF (357/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Flash Memory Array and Control
Table 12-1. Memory Map
Offset from
FLASH_BASE
(0x0000_0000)
Use
Flash A
Block
Flash B
Block
Flash A
Partition Block
Size
Flash B
Block
Size
Data
Width
0x0000_0000 Low-address space (Flash A)
L0
—
1
0x0000_4000
L1
—
0x0000_8000
L2
—
0x0000_C000
L3
—
0x0001_0000
L4
—
2
0x0001_4000
L5
—
0x0001_8000
L6
—
0x0001_C000
L7
—
0x0002_0000
L8
—
3
0x0003_0000
L9
—
0x0004_0000 Mid-address space (Flash A)
M0
—
4
0x0006_0000
M1
—
0x0008_0000 Low-address space (Flash B)
—
L0
5
0x000C_0000 Mid-address space (Flash B)
0x0010_0000 High-address space¹
—
M0
H0
H0
6
0x0018_0000
H1
H1
0x0020_0000
H2
H2
7
0x0028_0000
H3
H3
0x0030_0000
H4
H4
8
0x0038_0000
H5
H5
0x0040_0000 Reserved
0x00EF_C000 Shadow Block (Flash B space) (see Table 12-2) —
S0
All²
0x00FF_C000 Shadow Block (Flash A space) (see Table 12-2) S0
—
0x0100_C000 Reserved
1 _{See Figure 12-1 to see how Flash A and Flash B, together, make up the high address space.}
2 _{For read while write operations, the shadow row behaves as if it is in all partitions.}
16K
—
128
16K
—
128
16K
—
128
16K
—
128
16K
—
128
16K
—
128
16K
—
128
16K
—
128
64K
—
128
64K
—
128
128K
—
128
128K
—
128
—
256K 128
—
256K 128
256K 256K 256
256K 256K 256
256K 256K 256
256K 256K 256
256K 256K 256
256K 256K 256
—
16K 128
16K
—
128
Table 12-2 shows the shadow block space. The 16K region of the Shadow Block for Flash B space mirrors
from 0x00E0_0000 to 0x00EF_FFFF and Shadow A mirrors every 16K from 0x00F0_0000 through
0x00FF_FFFF. Mirrored operation is not guaranteed
Flash_A and Flash_B arrays have separate configuration and control registers for programming and erase
operations. Flash bus configuration registers are common to both arrays.
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
12-5