PXR40RM Datasheet, PDF (907/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Deserial Serial Peripheral Interface (DSPI)
25.4.6.4 Delay after Transfer (t_DT)
The Delay after Transfer is the length of time between negation of the PCS signal for a frame and the
assertion of the PCS signal for the next frame. See Figure 25-29 for an illustration of the Delay after
Transfer. The PDT and DT fields in the DSPI_CTARx registers select the Delay after Transfer by the
formula in the DT[0:3] field description. Table 25-31 shows an example of how to compute the Delay after
Transfer.
Table 25-31. Delay after Transfer Computation Example
PDT
0b01
Prescaler
3
DT
0b1110
Scaler
32768
f_periph
100 MHz
Delay after Transfer
0.98 ms
When in non-continuous clock mode the t_DT delay is configurable as outlined in the DSPI_CTARx
registers. When in continuous clock mode and TSB is not enabled the delay is fixed at 1 SCK period. When
in TSB and continuous mode the delay is programmed as outlined in the DSPI_CTARx registers but in the
event that the delay does not coincide with an SCK period in duration the delay is extended to the next
SCK active edge. Table 25-32 shows an example of how to compute the Delay after Transfer with the clock
period of SCK defined as T_SCK. The values calculated assume 1 TSCK period = 4 ipg_clk.
Table 25-32. Delay after Transfer Computation Example in TSB Configuration
t_DT1
(Tsck)
0²
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
1
1
2
4
8
16
32
64
128
256
512
1024
2048
4096
8192
16384
PDT field
1
2
2
3
6
12
24
48
96
192
384
768
1536
3072
6144
12288
24576
49152
3
5
10
20
40
80
160
320
640
1280
2560
5120
10240
20480
40960
81920
3
4
7
14
28
56
112
224
448
896
1792
3584
7168
14336
28672
57344
114688
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
25-47