PXR40RM Datasheet, PDF (491/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Error Correction Status Module (ECSM)
Offset: ECSM_BASE_ADDR + 0x0060
Access: User read-only
0
R
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
REAR
W
Reset U¹
U
U
U
U
U
U
U
U
UU U
U
U
U
U
16
R
W
Reset U
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
REAR
U
U
U
U
U
U
U
U
UU U
U
U
U
U
1 _{U = undefined at reset}
Figure 17-10. RAM ECC Address (ECSM_REAR) Register
Table 17-11. ECSM_REAR Field Descriptions
Field
Description
0–31 RAM ECC Address Register. Contains the faulting access address of the last, properly-enabled RAM ECC event.
REAR
17.2.2.13 RAM ECC Syndrome Register (ECSM_RESR)
The ECSM_RESR is an 8-bit register for capturing the error syndrome of the last properly enabled ECC
event in the RAM memory. Depending on the state of the ECC configuration register, an ECC event in the
RAM causes the address, attributes, and data associated with the access to be loaded into the
ECSM_REAR, ECSM_RESR, ECSM_REMR, ECSM_REAT and ECSM_REDR registers, and the
appropriate flag (R1BC or RNCE) in the ECC status register to be asserted.
This register is read-only; any attempted write is ignored. See Figure 17-11 and Table 17-12 for the RAM
ECC syndrome register definition.
Offset: ECSM_BASE_ADDR + 0x0065
0
1
2
3
4
5
R
RESR[0:7]
W
Reset
U¹
U
U
U
U
U
Figure 17-11. RAM ECC Syndrome (ECSM_RESR) Register
1 _{U = undefined at reset}
Access: User read-only
6
7
U
U
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
17-13