PXR40RM Datasheet, PDF (784/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Modular Input/Output Subsystem (eMIOS200)
At OPWFMB mode entry, the output flip-flop is set to the value of the EDPOL bit in the EMIOS_CCR[n]
register.
To provide smooth and consistent channel operation, this mode differs substantially from the OPWFM
mode. The main differences reside in the A1 and B1 registers update, on the delay from the A1 match to
the output pin transition, and on the internal counter values, which range from 0x00_0001 up to the value
in register B1.
When entering OPWFMB mode (coming out of GPIO mode), if the internal counter value is not within
that range, then the B match will not occur, causing the channel internal counter to wrap at the maximum
counter value which is 0xFF_FFFF. After the counter wrap occurs, the value returns to 0x00_0001 and the
counter resumes normal OPWFMB mode operation. Thus in order to avoid the counter wrap condition,
make sure its initial value is within the range between 0x00_0001 and the B1 register value the OPWFMB
mode is entered.
When a match on comparator A occurs, the output register is set to the value of EDPOL. When a match
on comparator B occurs, the output register is set to the complement of EDPOL. B1 match also causes the
internal counter to transition to 0x00_0001, thus restarting the counter cycle.
Only values greater than 0x00_0001 are allowed to be written to the B1 register. Loading values other than
those leads to unpredictable results.
Figure 23-40 shows the operation of the OPWFMB mode regarding output pin transitions and A1/B1
registers match events. The output pin transition occurs when the A1 or B1 match signal is deasserted,
which is indicated by the A1 match negative edge detection signal. If register A1 is set to 0x00_0004, the
output pin transitions four counter periods after the cycle has started, plus one system clock cycle. In the
example shown in Figure 23-40 the internal counter prescaler has a ratio of two.
Prescaler Ratio = 2
EDPOL = 0
System Clock
Prescaler
EMIOS_CCNTR[n]
1
A1 Value 0x000004
B1 Value 0x000008
A1 Match
8
4
5
A1 Match
Negative Edge
Detection
Time
A1 Match Negative Edge Detection
B1 Match
B1 Match Negative Edge Detection
B1 Match
Negative Edge
Detection
Output Pin
Figure 23-40. OPWFMB A1 and B1 Match to Output Register Delay
23-44
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor