PXR40RM Datasheet, PDF (1191/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Time Processing Unit (eTPU2)
This bit selects the direction of the coherent data transfer.
1 = Write operation. Data transfer is from the PB to the selected SDM address.
0 = Read operation. Data transfer is from the selected SDM address to the PB.
PARM0[0:6], PARM1[0:6] — Channel Parameter number 0/number 1
These fields in concatenation with CTBASE[0:4] determine the word address offset (from the SDM
base) of the parameters that are destination or source (defined by WR) of the coherent transfer. The
word SDM address offset of the parameters are {CTBASE, PARM0/1}.Note that PARM0 and
PARM1 allow non-contiguous parameters to be transferred coherently. The parameter pointed by
{CTBASE, PARM0} is the first transferred.
29.2.5.3 ETPUMISCCMPR - eTPU MISC Compare Register
ETPUMISCCMPR holds the 32-bit signature expected from the whole SCM array. This register must be
written by the host with the 32-bit word to be compared against the calculated signature at the end of the
MISC cycle. This register is global to both eTPU Engines. For more detail see Section 29.3.6.1, SCM Test
- Multiple Input Signature Calculator.
Base + 0x00C
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
ETPUMISCCMP[0:15]
W
RESET: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
ETPUMISCCMP[16:31]
W
RESET: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 29-5. ETPUMISCCMPR Register
ETPUMISCCMP[0:31] — Expected Multiple Input Signature Register value
See Section 29.3.6.1, SCM Test - Multiple Input Signature Calculator.
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
29-23