PXR40RM Datasheet, PDF (548/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Direct Memory Access Controller (eDMA)
21.3.2.6 eDMA Clear Enable Request Register (EDMA_x_CERQR)
NOTE
Any reference to EDMA_A_[register_name] should be ignored when using
eDMA_B. That register does not exist in eDMA_B. Registers that exist in
both eDMA_A and eDMA_B are indicated with a register name of format
EDMA_x_[register_name].
The EDMA_x_CERQR provides a simple memory-mapped mechanism to clear a given bit in the
EDMA_A_ERQRH or EDMA_x_ERQRL to disable the DMA request for a given channel. The data value
on a register write causes the corresponding bit in the EDMA_A_ERQRH or EDMA_x_ERQRL to be
cleared. Setting bit 1 (CERQ[0]) provides a global clear function, forcing the entire contents of
EDMA_A_ERQRH and EDMA_x_ERQRL to be zeroed, disabling all eDMA request inputs. Reads of this
register return all zeroes.
If bit 0 is set, the CERQ command is ignored. This allows multiple byte registers to be written as a 32-bit
word. Reads of this register return all zeroes.
Offset: EDMA_x_BASE + 0x0019
Access: User write-only
0
1
2
3
4
5
6
7
R0
0
0
0
0
0
0
0
W NOP
CERQ[0:6]
Reset 0
0
0
0
0
0
0
0
Figure 21-10. eDMA Clear Enable Request Register (EDMA_x_CERQR)
Table 21-9. EDMA_x_CERQR Field Descriptions
Field
0
NOP
1–7
CERQ
Description
No operation.
0 Normal operation.
1 No operation, ignore bits 1–7.
Clear Enable Request.
0–31 (63 for eDMA_A) Clear corresponding bit in EDMA_A_ERQRH or EDMA_x_ERQRL.
64–127 Clear all bits in EDMA_A_ERQRH and EDMA_x_ERQRL.
Bit 2 (CERQR[1]) is not used on eDMA_B.
21-24
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor