PXR40RM Datasheet, PDF (596/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

FlexRay Communication Controller (FLEXRAY)
reset conditions are mentioned in the detailed description of the register. The additional reset conditions
are explained in Table 22-5.
Table 22-5. Additional Register Reset Conditions
Condition
Protocol RUN Command
Message Buffer Disable
Description
The register field is reset when the application writes to RUN command “0101” to the
POCCMD field in the Protocol Operation Control Register (POCR).
The register field is reset when the application has disabled the message buffer.
This happens when the application writes 1 to the message buffer disable trigger bit
MBCCSRn[EDT] while the message buffer is enabled (MBCCSn[EDS] = 1) and the
controller grants the disable to the application by clearing the MBCCSRn[EDS] bit.
22.5.2.2 Register Write Access
This section describes the write access restriction terms that apply to all registers.
22.5.2.2.1 Register Write Access Restriction
For each register bit and register field, the write access conditions are specified in the detailed register
description. A description of the write access conditions is given in Table 22-6. If, for a specific register
bit or field, none of the given write access conditions is fulfilled, any write attempt to this register bit or
field is ignored without any notification. The values of the bits or fields are not changed. The condition
term [A or B] indicates that the register or field can be written to if at least one of the conditions is fulfilled.
Table 22-6. Register Write Access Restrictions
Condition
Any Time
Disabled Mode
Normal Mode
POC:config
MB_DIS
MB_LCK
Indication
—
MCR[MEN] = 0
MCR[MEN] = 1
PSR0[PROTSTATE] = POC:config
MBCCSR[EDS] = 0
MBCCSRn[LCKS] = 1
Description
No write access restriction.
Write access only when the controller is in Disabled Mode.
Write access only when the controller is in Normal Mode.
Write access only when the Protocol is in the POC:config state.
Write access only when the related Message Buffer is disabled.
Write access only when the related Message Buffer is locked.
22.5.2.2.2 Register Write Access Requirements
All registers can be accessed with 8-bit, 16-bit and 32-bit wide operations. For some of the registers, at
least a 16-bit wide write access is required to ensure correct operation. This write access requirement is
stated in the detailed register description for each register affected
22.5.2.2.3 Internal Register Access
The following memory mapped registers are used to access multiple internal registers.
• Strobe Signal Control Register (STBSCR)
• Slot Status Selection Register (SSSR)
• Slot Status Counter Condition Register (SSCCR)
• Receive Shadow Buffer Index Register (RSBIR)
22-12
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor