PXR40RM Datasheet, PDF (863/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Deserial Serial Peripheral Interface (DSPI)
• Programmable transfer attributes on a per-frame basis:
— Eight transfer attribute registers
— Serial clock with programmable polarity and phase
— Various programmable delays
— Programmable serial frame size of 4 to 32 bits, expandable by software control
— Continuously held chip select capability
• 8 Peripheral Chip Selects, expandable to 256 with external demultiplexer
• Deglitching support for up to 128 Peripheral Chip Select with external demultiplexer
• DMA support for adding entries to TX FIFO and removing entries from RX FIFO:
— TX FIFO is not full (TFFF)
— RX FIFO is not empty (RFDF)
• 6 Interrupt conditions:
— End of queue reached (EOQF)
— TX FIFO is not full (TFFF)
— Transfer of current frame complete (TCF)
— Attempt to transmit with an empty Transmit FIFO (TFUF)
— RX FIFO is not empty (RFDF)
— Frame received while Receive FIFO is full (RFOF)
• Modified SPI transfer formats for communication with slower peripheral devices
• Power-saving architectural features
— Support for Stop Mode
The DSPI also supports pin reduction through serialization and deserialization.
• Two sources of serialized data:
— DSPI memory-mapped register
— Parallel Input signals
• Deserialized data is provided as Parallel Output signals and as bits in a memory-mapped register
• Transfer initiation conditions:
— Continuous
— Edge sensitive hardware trigger
— Change in data
• Support for parallel and serial chaining of up to four DSPI blocks
• Pin serialization/deserialization with interleaved SPI frames for control and diagnostics
• Continuous serial communications clock
• Enhanced DSI logic to implement a 32 bits Timed Serial Bus (TSB) configuration, supporting the
Micro Second Bus downstream frame format.
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
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