PXR40RM Datasheet, PDF (549/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Direct Memory Access Controller (eDMA)
21.3.2.7 eDMA Set Enable Error Interrupt Register (EDMA_x_SEEIR)
NOTE
Any reference to EDMA_A_[register_name] should be ignored when using
eDMA_B. That register does not exist in eDMA_B. Registers that exist in
both eDMA_A and eDMA_B are indicated with a register name of format
EDMA_x_[register_name].
The EDMA_x_SEEIR provides a memory-mapped mechanism to set a given bit in the EDMA_A_EEIRH
or EDMA_x_EEIRL to enable the error interrupt for a given channel. The data value on a register write
causes the corresponding bit in the EDMA_A_EEIRH or EDMA_x_EEIRL to be set. Setting bit 1
(SEEI[0]) provides a global set function, forcing the entire contents of EDMA_A_EEIRH or
EDMA_x_EEIRL to be asserted. Reads of this register return all zeroes.
If bit 0 is set, the SEEI command is ignored. This allows multiple byte registers to be written as a 32-bit
word. Reads of this register return all zeroes.
Offset: EDMA_x_BASE + 0x001A
Access: User write-only
0
1
2
3
4
5
6
7
R0
0
0
0
0
0
0
0
W NOP
SEEI[0:6]
Reset 0
0
0
0
0
0
0
0
Figure 21-11. eDMA Set Enable Error Interrupt Register (EDMA_x_SEEIR)
Table 21-10. EDMA_x_SEEIR Field Descriptions
Field
0
NOP
1–7
SEEI[0:6]
Description
No operation.
0 Normal operation.
1 No operation, ignore bits 1–7.
Set Enable Error Interrupt.
0–31 (63 for eDMA_A) Set corresponding bit in EDMA_A_EIRRH or EDMA_x_EIRRL.
64–127 Set all bits in EDMA_A_EIRRH or EDMA_x_EEIRL.
Bit 2(SEEIR[1]) is not used on eDMA_B.
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
21-25