PXR40RM Datasheet, PDF (664/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

FlexRay Communication Controller (FLEXRAY)
A receive FIFO consists of a set of physical message buffers in the flexray memory and a set of receive
FIFO control registers located in dedicated registers. The structure of a receive FIFO is given in
Figure 22-106.
The connection between the receive FIFO control registers and the set of physical message buffers is
established by the Receive FIFO Start Index Register (RFSIR), the Receive FIFO Depth and Size Register
(RFDSR), and the Receive FIFO A Read Index Register (RFARIR) / Receive FIFO B Read Index Register
(RFBRIR). The system memory base address SMBA is defined by the system memory base address
register selected by the FIFO address mode bit MCR[FAM].
The start byte address SADR_MBHF[1] of the first message buffer header field that belongs to the receive
FIFO in the flexray memory is determined according to Equation 22-5.
SADR_MBHF[1] = (10 * RFSIR[SIDX]) + SMBA
Eqn. 22-5
The start byte address SADR_MBHF[n] of the last message buffer header field that belongs to the receive
FIFO in the flexray memory is determined according to Equation 22-6.
SADR_MBHF[n] = (10 * (RFSIR[SIDX] + RFDSR[FIFO_DEPTH])) + SMBA
NOTE
All message buffer header fields assigned to a receive FIFO must be a
contiguous region.
Eqn. 22-6
22-80
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor